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MP8798
CMOS Very Low Power, 1 MSPS 10-Bit Analog-to-Digital Converter with 4-Channel Mux
FEATURES
* * * * * * * * * * * * 10-Bit Resolution 4-Channel Mux Sampling Rates from <1 kHz to 1 MHz Very Low Power CMOS - 30 mW (typ) Power Down; Lower Consumption - 3 mW (typ) Input Range between GND and VDD No S/H Required for Analog Signals less than 100 kHz No S/H Required for CCD Signals less than 1 MHz Single Power Supply (4 to 6 Volts) Latch-Up Free High ESD Protection: 4000 Volts Minimum 3 V Version: MP87L98
BENEFITS
* * * * * * * * Reduced Board Space (Small Package) Reduced External Parts, No Sample/Hold Needed Suitable for Battery & Power Critical Applications Designer can Adapt Input Range & Scaling P/DSP Interface and Control Applications High Resolution Imaging - Scanners & Copiers Wireless Digital Communications Multiplexed Data Acquisition
APPLICATIONS
GENERAL DESCRIPTION
The MP8798 is a flexible, easy to use, precision 10-bit Analog-to-Digital Converter with 4-channel mux that operates over a wide range of input and sampling conditions. The MP8798 can operate with pulsed "on demand" conversion operation or continuous "pipeline" operation for sampling rates up to 1 MHz. The elimination of the S/H, requirements, very low power, and small package size offer the designer a low cost solution. No sample and hold is required for charge couple device applications, up to 1 MHz, or multiplexed input applications when the signal source bandwidth is limited to 100 kHz. The input architecture of the MP8798 allows direct interface to any analog input range between AGND and AVDD (0 to 2 V, 1 to 4 V, 0 to 5 V, etc.). The user simply sets VREF(+) and VREF(-) to encompass the desired input range. Scaled reference resistor tap 1/2 R allows for customizing the transfer curve as well as providing a 1/2 span reference voltage. Digital outputs are CMOS and TTL compatible. The MP8798 uses a two-step flash technique. The first segment converts the 4 MSBs and consists of 15 autobalanced comparators, latches, an encoder, and buffer storage registers. The second segment converts the remaining 6 LSBs. When the power down input is "high", the data outputs DB9 to DB0 hold the current values and VREF(-) is disconnected from VREF1(-). The power consumption during the power down mode is approximately 3mW. Specified for operation over the commercial / industrial (-40 to +85C) temperature range, the MP8798 is available in plastic dual-in-line (PDIP), surface mount (SOIC), and shrink small outline (SSOP) packages.
ORDERING INFORMATION
Package Type
SOIC PDIP SSOP
Temperature Range
-40 to +85C -40 to +85C -40 to +85C
Part No.
MP8798AS MP8798AN MP8798AQ
DNL (LSB)
1 1 1
INL (LSB)
2 2 2
Rev. 3.00 1
MP8798
SIMPLIFIED BLOCK AND TIMING DIAGRAM
AVDD DVDD
Coarse Comparators B VREF(+) 1/2 R VREF(-) VREF1(-) PD Ladder
4
Adder
5 OFW CLK DB9-DB0 OFW
S N
B
Fine Resolution Comparators
DFF 6
DB9-DB0 10
N-1 N-1
N N
CLK AIN1 AIN2 AIN3 AIN4 S 1 or 4 MUX 4 WR 2 to 4 Decoder Latch A1 A0
AGND DGND
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
DB3 DB4 DB5 DB6 DB7 DGND DVDD WR A1 A0 CLK DB8 DB9 OFW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
DB2 DB1 DB0 PD AVDD AGND AIN4 AIN3 AIN2 AIN1 1/2 R VREF1(-) VREF(-) VREF(+)
DB3 DB4 DB5 DB6 DB7 DGND DVDD WR A1 A0 CLK DB8 DB9 OFW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DB2 DB1 DB0 PD AVDD AGND AIN4 AIN3 AIN2 AIN1 1/2 R VREF1(-) VREF(-) VREF(+)
28 Pin PDIP (0.300") NN28
28 Pin SOIC (Jedec, 0.300") - S28 28 Pin SSOP - A28
Rev. 3.00 2
MP8798
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME DB3 DB4 DB5 DB6 DB7 DGND DVDD WR A1 A0 CLK DB8 DB9 OFW DESCRIPTION Data Output Bit 3 Data Output Bit 4 Data Output Bit 5 Data Output Bit 6 Data Output Bit 7 Digital Ground Digital VDD Write (Active Low) Address 1 Input Address 0 Input Clock Input Data Output Bit 8 Data Output Bit 9 (MSB) Overflow Output PIN NO. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME VREF(+) VREF(-) VREF1(-) 1/2 R AIN1 AIN2 AIN3 AIN4 AGND AVDD PD DB0 DB1 DB2 DESCRIPTION Upper Reference Voltage Lower Reference Voltage Lower Reference Voltage Reference Ladder Tap Analog Signal Input 1 Analog Signal Input 2 Analog Signal Input 3 Analog Signal Input 4 Analog Ground Analog VDD Power Down Data Output Bit 0 (LSB) Data Output Bit 1 Data Output Bit 2
TRUTH TABLE FOR INPUT CHANNEL SELECTION
WR 0 0 0 0 1
A1 0 0 1 1 X
A0 0 1 0 1 X
SELECTED ANALOG INPUT AIN1 AIN2 AIN3 AIN4 Previous selection
Note: WR, A1, A0 are internally connected to GND through 500k resistance.
Rev. 3.00 3
MP8798
ELECTRICAL CHARACTERISTICS TABLE
Unless Otherwise Specified: AVDD = DVDD = 5 V, FS = 1 MHz (50% Duty Cycle), VREF(+) = 4.6, VREF(-) = AGND, TA = 25C
Parameter KEY FEATURES Resolution Sampling Rate ACCURACY2 Differential Non-Linearity Integral Non-Linearity Zero Scale Error Full Scale Error REFERENCE VOLTAGES Positive Ref. Voltage Negative Ref. Voltage Differential Ref. Voltage5 Ladder Resistance Ladder Temp. Coefficient1 Ladder Switch Resistance1 Ladder Switch Off Leakage1 ANALOG INPUT1 Input Bandwidth Input Voltage Range7 Input Capacitance3 Aperture Delay DIGITAL INPUTS Logical "1" Voltage Logical "0" Voltage Leakage Currents CLK PD, (Internal Res to DGND) Input Capacitance Clock Timing (See NO TAG)1 Clock Period Rise & Fall Time4 "High" Time6 "Low" Time6 VIH VIL IIN 2.0 0.8 100 30 5 TS tR, tF tB tS 1000 250 150 10 500,000 500,000 V V A A pF ns ns ns ns VIN=DGND to DVDD 100 VIN CIN tAP VREF(-) 60 35 VREF(+) 45 kHz V pF ns VREF(+) VREF(-) DVREF RL RTCO ILKG-SW AVDD AGND 0.5 525 AVDD 900 V V V ppm/C nA DNL INL EZS EFS 3/4 1 2 LSB LSB LSB LSB 10 .001 Bits MHz Symbol Min 25C Typ Max Units Test Conditions/Comments
FS
1
For Rated Performance
+0.50 -2.5
Best Fit Line (Max INL - Min INL)/2 Reference from VREF(+) to VREF(-)
675 2000 12 50
-5
Rev. 3.00 4
MP8798
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Parameter DIGITAL OUTPUTS Logical "1" Voltage Logical "0" Voltage Tristate Leakage Data Hold Time (See NO TAG)1 Data Valid Delay1 Write Pulse Width1 Multiplexer Address Setup Time1 Multiplexer Address Hold Time1 Delay from WR to Multiplexer1 Enable Power Down Time1 Power Up Time1 POWER SUPPLIES8 Power Down (IDD) Operating Voltage (AVDD, DVDD) Current (AVDD + DVDD) IPD-DD VDD IDD 0.6 5 6 1.2 6.5 10 mA V mA VOH VOL IOZ tHLD tDL tWR tAS tAH tMUXEN1 tPD tPU DVDD-0.5 0 30 35 40 80 0 80 300 200 0.4 5 35 45 V V A ns ns ns ns ns ns ns ns Symbol Min 25C Typ Max Units Test Conditions/Comments COUT=15 pF ILOAD = 2 mA ILOAD = 4 mA VOUT = 0 to DVDD
4
VIN = 2 V
NOTES: Guaranteed. Not tested. Tester measures code transition voltages by dithering the voltage of the analog input (VIN). The difference between the measured code width and the ideal value (VREF/1024) is the DNL error (see NO TAG). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (See Figure 7.). 3 See VIN input equivalent circuit (see Figure 9.). 4 Clock specification to meet aperture specification (tAP). Actual rise/fall time can be less stringent with no loss of accuracy. 5 Specified values guarantee functional device. Refer to other parameters for accuracy. 6 System can clock MP8798 with any duty cycle as long as all timing conditions are met. 7 Input range where input is converted correctly into binary code. Input voltage outside specified range converts to zero or full scale output. 8 DVDD and AVDD are connected through the silicon substrate. Connect together at the package.
1 2
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2
VDD (to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VREF(+) & VREF(-) . . . . . . . . . . . . . . GND -0.5 to VDD +0.5 V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 to VDD +0.5 V All Inputs . . . . . . . . . . . . . . . . . . . . . GND -0.5 to VDD +0.5 V All Outputs . . . . . . . . . . . . . . . . . . . GND -0.5 to VDD +0.5 V Storage Temperature . . . . . . . . . . . . . . . . . . . -65 to +150C Lead Temperature (Soldering 10 seconds) . . . . . . . +300C Package Power Dissipation Rating to 75C SOIC, PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . 14mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND. Rev. 3.00 5
MP8798
tS CLOCK
SAMPLE N-1 AUTO BALANCE SAMPLE N AUTO BALANCE SAMPLE N+1
tR
tB
tF VIH VIL
when S disconnects the latches from the comparators. This delay is called aperture delay (tAP). The coarse comparators make the first pass conversion and selects a ladder range for the fine comparators. The fine comparators are connected to the selected range during the next B phase.
ANALOG INPUT VOH DATA VOL
TS VIN
S
B
S
Latch
VTAP N-1 tDL tHLD Ref Ladder
B S
COARSE COMPARATOR
S
B
Latch
Figure 1. MP8798 Timing Diagram
VIN VTAP
THEORY OF OPERATION
Analog-to-Digital Conversion
The MP8798 converts analog voltages into 1024 digital codes by encoding the outputs of 15 coarse and 67 fine comparators. Digital logic is used to generate the overflow bit. The conversion is synchronous with the clock and it is accomplished in 2 clock periods. The reference resistance ladder is a series of 1025 resistors. The first and the last resistor of the ladder are half the value of the others so that the following relations apply: RREF = 1024 R VREF = VREF(+) - VREF(-) = 1024 LSB The clock signal generates the two internal phases, B (CLK high) and S (CLK low = sample) (See Figure 2.). The rising edge of the CLK input marks the end of the sampling phase (S). Internal delay of the clock circuitry will delay the actual instant
Selected Range
B
FINE COMPARATOR
Figure 2. MP8798 Comparators
AIN Sampling, Ladder Sampling, and Conversion Timing
Figure 3. shows this relationship as a timing chart. AIN sampling, ladder sampling and output data relationships are shown for the general case where the levels which drive the ladder need to change for each sampled AIN time point. The ladder is referenced for both last AIN sample and next AIN sample at the same time. If the ladder's levels change by more than 1 LSB, one of the samples must be discarded. Also note that the clock low period for the discarded AIN can be reduced to the minimum tS time of 150 ns.
Hold Reference Value Past Clock Change for tAP Time
Short Cycle Sample will be discarded tS
External Update References Clock Internal AIN Sample Window Ladder Sample Window (MSB Bank) Ladder Compare (LSB Bank) External DATA
Settle by Clock Update Time Reference Stable Time - For Sample AIN2 Reference Stable Time - For Sample AIN1 AINX1
Sample AIN1
Sample AIN2
FB
AINX0 Sample Ladder for AIN1
FS
Sample AIN1
FB
Not Used
FS
FB
FS
Sample AIN2
AINX1 Sample Ladder for AINX1 Sample Ladder for AIN2
Sample Ladder for AINX2
Compare Ladder V/S AINX0
Compare Ladder V/S AIN1
Compare Ladder V/S AINX1
Compare Ladder V/S AIN2
DATA AIN0
DATA AINX0 Not Used
DATA AIN1
DATA AINX1 Not Used
Figure 3. AIN Sampling, Ladder Sampling & Conversion Timing
Rev. 3.00 6
MP8798
Accuracy of Conversion: DNL and INL
DNL LSB V(N+1) Analog Input V(N) DIGITAL CODES 0.5 LSB N+1 0.5 LSB Output Codes N N-1 OFW = 0 1 LSB 3FE 001 000 LSB V VREF(-) V001 V002 V3FE V3FF V0FW VREF(+) 002 3FD 3FF OFW = 1 (N+1) Code Width = V(N+1) - V(N) LSB = [ VREF(+) - VREF(-) ] / 1024 DNL(N) = [ V(N+1) - V(N) ] - LSB
The transfer function for an ideal A/D converter is shown in Figure 4.
Figure 5. DNL Measurement On Production Tester
The formulas for Differential Non-linearity (DNL), Integral Non-Linearity (INL) and zero and full scale errors (EZS, EFS) are:
Figure 4. Ideal A/D Transfer Function
The overflow transition (VOFW) takes place at: VIN = VOFW = VREF(+) - 0.5 LSB The first and the last transitions for the data bits take place at: VIN = V001 = VREF(-) + 0.5 LSB VIN = V3FF = VREF(+) - 1.5 LSB LSB = VREF / 1024 = (V3FF - V001) / 1022 Note that the overflow transition is a flag and has no impact on the data bits. In a "real" converter the code-to-code transitions don't fall exactly every VREF/1024 volts. A positive DNL (Differential Non-Linearity) error means that the real width of a particular code is larger than 1 LSB. This error is measured in fractions of LSBs. A Max DNL specification guarantees that ALL code widths (DNL errors) are within the stated value. A specification of Max DNL = + 0.5 LSB means that all code widths are within 0.5 and 1.5 LSB. If VREF = 4.608 V then 1 LSB = 4.5 mV and every code width is within 2.25 and 6.75 mV.
DNL (001) = V002 - V001 - LSB ::: DNL (3FE) = V3FF - V3FE - LSB EFS (full scale error) = V3FF - [VREF(+) -1.5 LSB] EZS (zero scale error) = V001 - [VREF(-) + 0.5 LSB]
DIGITAL CODES 0.5 LSB EZS 002 001 000 VREF(-) V001 V002 V3FE V V3FF VREF(+) 3FE
1.5 LSB EFS 3FF
Figure 6. Real A/D Transfer Curve
Figure 6. shows the zero scale and full scale error terms.
Rev. 3.00 7
MP8798
Figure 7. gives a visual definition of the INL error. The chart shows a 3-bit converter transfer curve with greatly exaggerated DNL errors to show the deviation of the real transfer curve from the ideal one.
After a tester has measured all the transition voltages, the computer draws a line parallel to the ideal transfer line. By definition the best fit line makes equal the positive and the negative INL errors. For example, an INL error of -1 to +2 LSB's relative to the Ideal Line would be +1.5 LSB's relative to the best fit line.
Output Codes 7 Real Transfer Line 6 5 INL 4 3 2 1 LSB Ideal Transfer Line EFS DATA b. Single sampling N
A system will clock the MP8798 continuously or it will give clock pulses intermittently when a conversion is desired. The timing of Figure 8a shows normal operation, while the timing of Figure 8b keeps the MP8798 in balance and ready to sample the analog input.
CLOCK DATA N N+1 N a. Continuous sampling N+1
Best Fit Line CLOCK N BALANCE
Figure 8. Relationship of Data to Clock Analog Input
The MP8798 has very flexible input range characteristics. The user may set VREF(+) and VREF(-) to two fixed voltages and then vary the input DC and AC levels to match the VREF range. Another method is to first design the analog input circuitry and then adjust the reference voltages for the analog input range. One advantage is that this approach may eliminate the need for external gain and offset adjust circuitry which may be required by fixed input range A/Ds. The MP8798's performance is optimized by using analog input circuitry that is capable of driving the AIN input. Figure 9. shows the equivalent circuit for AIN.
40 R Series 40 AIN 15 pF 4 1 pF 4 Control Channel Selection 10 pF 300 R MUX 500 87 pF
EZS
Analog Input (Volt)
Figure 7. INL Error Calculation
Clock and Conversion Timing
VDD
S
60 pF
87 pF 160
S
B
+ 4 pF 1/2 [ VREF(+) + VREF(-) ]
Figure 9. Analog Input Equivalent Circuit
Rev. 3.00 8
MP8798
Analog Input Multiplexer
The MP8798 includes a 4-channel analog input multiplexer. The relationship between the clock, the multiplexer address, the WR and the output data is shown in Figure 10.
Digital Interfaces
The logic encodes the outputs of the comparators into a binary code and latches the data in a D-type flip-flop for output.
Clock
Sample N Old Address
Sample M New Address
Sample M+1
The functional equivalent of the MP8798 (Figure 12.) is composed of: 1) Delay stage (tAP) from the clock to the sampling phase (S). 2) An ideal analog switch which samples VIN. An ideal A/D which tracks and converts VIN with no delay. 4) A series of two DFF's with specified hold (tHLD) and delay (tDL) times. tAP, tHLD and tDL are specified in the Electrical Characteristics table. 3)
tCLKS2 WR tAS
tWR
tCLKH2
tAH
Address
DB0-DB9
MUXEN (Internal Signal)
Reference Voltages
The input/output relationship is a function of VREF: AIN = VIN - VREF(-) VREF = VREF(+) - VREF(-) DATA = 1023 (AIN/VREF) A system can increase total gain by reducing VREF.
Rev. 3.00 9
EEEEEEEEEE EE EEEEEEEEEE EE
N-2 Valid N-1 Valid Old Address N Valid Old Address M Valid New Address
tCLKS2 = tCLKH2 = 0
Figure 10. MUX Address Timing
tAS A1, A0 WR tWR tMUXEN1
tAH VIN
S
A/D DQ DQ DB9-DB0
tAP MP8798 CLK N tHLD tDL DB9-DB0 N-1 N N+1
CLK
Figure 11. Analog MUX Timing
VIN
Figure 12. MP8798 Functional Equivalent Circuit and Interface Timing
MP8798
Power Down
Figure 13. shows the relationship between the clock, sampled AIN to output data relationship and the effect of power down.
CLK
SAMPLE N SAMPLE M SAMPLE M+1
VIN DB0-DB9
N-2 Valid N-1 Valid tCLKS1 N Valid tCLKH1
PD
tPD tPU
IDD, IVREF(+)
Figure 13. Power Down Timing Diagram
Rev. 3.00 10
CCCCCC CCCCCC
M Valid
MP8798
APPLICATION NOTES
C1 = 4.7 or 10F Tantalum C2 = 0.1F Chip Cap or low inductance capacitor RT = Clock Transmission Line Termination
+5 V
1 of 4
Buffer
C1A, C2A AVDD Z 100W AIN1 (Substrate)
C1D, C2D DVDD OFW DB9 - DB0
AIN
AIN4
Resistive Isolation of 50 to 100W
MP8798
WR A0 A1
Reference Voltage Source
+ C1 - C2 C1 C2
VREF(+) 1/2 R VREF(-)
CLK RT
VREF1(-) AGND DGND
Figure 14. Typical Circuit Connections
The following information will be useful in maximizing the performance of the MP8798. 1. All signals should not exceed AVDD +0.5 V or AGND -0.5 V or DVDD +0.5 V or DGND -0.5 V. 2. Any input pin which can see a value outside the absolute maximum ratings (AVDD or DVDD+0.5 V or AGND -0.5 V) should be protected by diode clamps (HP5082-2835) from input pin to the supplies. All MP8798 inputs have input protection diodes which will protect the device from short transients outside the supply ranges. 3. The design of a PC board will affect the accuracy of MP8798. Use of wire wrap is not recommended. 4. The analog input signal (VIN) is quite sensitive and should be properly routed and terminated. It should be shielded from the clock and digital outputs so as to minimize cross coupling and noise pickup. 5. The analog input should be driven by a low impedance (less than 50). 6. Analog and digital ground planes should be substantial and common at one point only. The ground plane should act as a Rev. 3.00 11
shield for parasitics and not a return path for signals. To reduce noise levels, use separate low impedance ground paths. DGND should not be shared with other digital circuitry. If separate low impedance paths cannot be provided, DGND should be connected to AGND next to the MP8798. 7. DVDD should not be shared with other digital circuitry to avoid conversion errors caused by digital supply transients. DVDD for the MP8798 should be connected to AVDD next to the MP8798. 8. DVDD and AVDD are connected inside the MP8798 through the N - doped silicon substrate. Any DC voltage difference between DVDD and AVDD will cause undesirable internal currents. 9. Each power supply and reference voltage pin should be decoupled with a ceramic (0.1F) and a tantalum (10F) capacitor as close to the device as possible. 10. The digital output should not drive long wires. The capacitive coupling and reflection will contribute noise to the conversion. When driving distant loads, buffers should be used. 100 resistors in series with the digital outputs in some applications reduces the digital output disruption of AIN.
MP8798
+5 V 5k
0.1F
100k
MP5010
+ -
+
-
Figure 15. Example of a Reference Voltage Source
+5 V +5 V
1 of 4
5 V + VIN -
R
R VREF(+) AVDD
AIN1 AIN4
DB0
VREF(-)
AGND
For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent. NOTE: High R values affect the input BW of ADC due to the (R CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a tradeoff between AIN settling time and power dissipation.
Figure 16. 5 V Analog Input
+5 V +5 V
1 of 4
10 V + VIN -
2R
R VREF(+) AVDD
AIN1 2R AIN4
DB0
VREF(-)
AGND
For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent. NOTE: High R values affect the input BW of ADC due to the (R CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a tradeoff between AIN settling time and power dissipation.
Figure 17. 10 V Analog Input
Rev. 3.00 12
MP8798
MP8798
VIN VIN VIN VIN
DAC8
AIN1 AIN2 AIN3 AIN4
@ Power Down write values to DAC 3, 2, 1 = DAC 4 to minimize power consumption.
Figure 18. A/D Ladder and AIN with Programmed Control (of VREF(+), VREF(-), 1/2 TAP.)
- - - -
Only AIN and Ladder detail shown.
+ + + +
DAC7
DAC6
DAC5
DAC4
VREF(+) 1/2 VREF(+)
DAC3
DAC1
DAC MP7641
VREF1(-)
Rev. 3.00 13
MP8798
PERFORMANCE CHARACTERISTICS
Graph 1. DNL vs. Sampling Frequency
Graph 2. INL vs. Sampling Frequency
Graph 3. Supply Current vs. Sampling Frequency
Graph 4. Power Down Current vs. Sampling Frequency
Graph 5. DNL vs. Reference Voltage
Rev. 3.00 14
Graph 6. DNL vs. Temperature
MP8798
Graph 7. Supply Current vs. Temperature
Graph 8. Power Down Current vs. Temperature
Graph 9. Reference Resistance vs. Temperature
Rev. 3.00 15
MP8798
28 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) NN28
S
28 1 Q1 D
15 14 E1 E A1
Seating Plane
A L B e B1
C
INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN 0.130 0.015 0.014 0.038 0.008 1.340 0.290 0.240 MAX 0.230 -- 0.023 0.065 0.015 1.485 0.325 0.310
MILLIMETERS MIN 3.30 0.381 0.356 0.965 0.203 34.04 7.37 6.10 MAX 5.84 -- 0.584 1.65 0.381 37.72 8.26 7.87
0.100 BSC 0.115 0 0.055 0.020 (1) 0.150 15 0.070 0.100
2.54 BSC 2.92 0 1.40 0.508 3.81 15 1.78 2.54
Q1 S Note:
The minimum limit for dimensions B1 may be 0.023" (0.58 mm) for all four corner leads only.
Rev. 3.00 16
MP8798
28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S28
D
28
15
E
H
14
h x 45 C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.701 0.292 MAX 0.104 0.0115 0.019 0.0125 0.711 0.299
MILLIMETERS MIN 2.464 0.127 0.356 0.231 17.81 7.42 MAX 2.642 0.292 0.483 0.318 18.06 7.59
0.050 BSC 0.400 0.010 0.016 0 0.410 0.016 0.035 8
1.27 BSC 10.16 0.254 0.406 0 10.41 0.406 0.889 8
Rev. 3.00 17
MP8798
28 LEAD SHRINK SMALL OUTLINE PACKAGE (SSOP) A28
D
28
15
E
H
1
14
C Seating Plane e B A1 L A
MILLIMETERS SYMBOL A A1 B C D E e H L MIN 1.73 0.05 0.20 0.13 10.07 5.20 MAX 2.05 0.21 0.40 0.25 10.40 5.38 MIN
INCHES MAX 0.081 0.008 0.016 0.010 0.409 0.212
0.068 0.002 0.008 0.005 0.397 0.205
0.65 BSC 7.65 0.45 0 8.1 0.95 8
0.0256 BSC 0.301 0.018 0 0.319 0.037 8
Rev. 3.00 18
MP8798 Notes
Rev. 3.00 19
MP8798
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 3.00 20

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